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?1 CXP912032 e95y30b86-ps cmos 16-bit single chip microcomputer description the CXP912032 is a cmos 16-bit micro-computer integrating on a single chip an a/d converter, serial interface with an incorporated buffer ram, high- precision timing pattern generation function, pulse cycle measurement circuit, pwm generator, general- purpose prescaler, vertical sync separation circuit, and a measurement circuit which measures the signals of capstan fg, drum fg/pg, reel fg and other servo systems with high precision, as well as basic configurations like a 16-bit cpu, rom, ram, and i/o port. this lsi also provides sleep/stop modes that enable lower power consumption. features an efficient instruction set as a controller ?direct addressing, numerous abbreviated forms, multiplication and division instructions instruction sets for c language and rtos ?highly quadratic instruction system, general-purpose register of 16-bit 8-pin 16-bank configuration minimum instruction cycle time 100ns at 20mhz operation incorporated rom capacity 128k bytes incorporated ram capacity 6144 bytes peripheral functions ?a/d converter 8-bit 12-channel successive approximation system, automatic scanning function, 8-stage (soft) + 4-stage (hard) fifo for conversion results (conversion time: 20s at 20mhz) ?serial interface buffer ram (128 bytes, supports high-speed transfer mode), 3 channels ?timers 8-bit timer/counter + 8-bit timer (with timing output), 1 channel 16-bit capture timer/counter (with timing output), 1 channel 16-bit timer, 4 channels ?high-precision timing pattern generator ppg for 27 pins, 42 stages (max.) ppg for 16 pins, 16 stages (max.) rtg for 5 pins, 3 channels ?pwm/da gate output pwm for 14 bits, 2 channels (repetitive frequency of 39.1khz, 20mhz) da gate pulse for 14 bits, 2 channels ?servo input control capstan fg, drum fg/pg, reel fg ?vsync separator ?frc capture unit 24-bit and 8-stage fifo ?pwm output 14 bits, 2 channels ?general-purpose prescaler 10 bits, 1 channel ?pulse cycle measurement circuit 1 channel with mask input general-purpose i/o 80 pins (max.; when all multi-purpose pins are used as general-purpose i/o.) interruption 28 factors, 28 vectors, multi-interruption and priority selection possible standby mode sleep/stop package 100-pin plastic qfp/lqfp, 104-pin plastic lfbga piggyback/evaluation chip cxp912000 100-pin ceramic qfp/lqfp sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 100 pin qfp (plastic) 100 pin lqfp (plastic) 104 pin lfbga (plastic) structure silicon gate cmos ic
? 2 CXP912032 v s s v d d c l o c k g e n e r a t o r / s y s t e m c o n t r o l l e r r a m 6 1 4 4 b y t e s s p c 9 0 0 c p u c o r e r o m 1 2 8 k b y t e s f i f o f r c c a p t u r e u n i t 5 1 0 4 s e r i a l i n t e r f a c e u n i t ( c h 0 ) r a m 8 - b i t t i m e r / c o u n t e r 0 8 - b i t t i m e r 1 v s y n c s e p a r a t o r p u l s e m e a s u r e u n i t s e r v o i n p u t c o n t r o l c a p s t a n d r u m r e e l 4 3 p m s k p m i p w m 3 p w m 2 d a 1 p w m 0 e x i 1 e x i 0 r f g 1 r f g 0 c f g s y n c 1 s y n c 0 t 2 c i n t t 1 e c 0 s c k 2 s o 2 s i 2 s c k 1 s o 1 s i 1 c s 1 r e a l t i m e p u l s e g e n e r a t o r n m i i n t 0 r s t 8 p o r t a 8 p o r t b 8 p o r t c 8 p o r t d p o r t e 4 p o r t f p o r t g 8 p o r t h p o r t i e x t a l a x t a l p r e s c a l e r 1 4 - b i t p w m / d a g e n e r a t o r ( 2 c h ) s e r i a l i n t e r f a c e u n i t ( c h 1 ) c h 0 8 p o r t j r t o 0 t o r t o 4 p p o 1 0 0 t o p p o 1 0 9 1 6 - b i t t i m e r ( 4 c h ) p r o g r a m m a b l e p a t t e r n g e n e r a t o r r a m ( c h 1 ) c h 1 c h 2 f i f o f i f o a / d c o n v e r t e r 4 3 2 i n t 1 i n t 2 1 2 1 9 p p o 0 0 0 t o p p o 0 1 8 p r o g r a m m a b l e p r e s c a l e r p r o g r a m m a b l e p a t t e r n g e n e r a t o r r a m ( c h 0 ) 4 i n t e r r u p t c o n t r o l l e r 2 s e r i a l i n t e r f a c e u n i t ( c h 2 ) 1 6 - b i t c a p t u r e t i m e r / c o u n t e r r a m r a m 2 a n 0 t o a n 1 1 a v s s a v r e f a v d d 1 4 - b i t p w m g e n e r a t o r ( 2 c h ) d a 0 p w m 1 x o u t ( o s c o ) p c k / o s c i p o d p g d f g e c 2 s c k 0 s o 0 s i 0 c s 0 8 2 4 4 2 2 c s 2 4 6 block diagram
? 3 CXP912032 pin configuration 1 (top view) 100-pin qfp package p b 2 / p p o 0 1 0 p b 3 / p p o 0 1 1 p b 4 / p p o 0 1 2 p b 5 / p p o 0 1 3 p b 6 / p p o 0 1 4 p b 7 / p p o 0 1 5 p c 0 / p p o 0 1 6 p c 1 / p p o 0 1 7 p c 2 / p p o 0 1 8 p c 3 / r t o 0 p c 4 / r t o 1 p c 5 / r t o 2 p c 6 / r t o 3 p c 7 / r t o 4 v s s p d 0 / k s 0 p d 1 / k s 1 p d 2 / k s 2 p d 3 / k s 3 p d 4 / k s 4 p d 5 / k s 5 p d 6 / k s 6 p d 7 / k s 7 p e 0 p e 1 p e 2 p e 3 p e 4 p e 5 p e 6 p j 0 / a n 4 / k s 8 a v d d a v r e f a v s s a n 3 a n 2 a n 1 p i 7 / a n 0 v s s p i 6 / x o u t p i 5 / o s c o p i 4 / p c k / o s c i p i 3 / c s 2 / p o p i 2 / s c k 2 p i 1 / s o 2 p i 0 / s i 2 s c k 0 s o 0 s i 0 c s 0 p h 7 / c f g p h 6 / d f g p h 5 / d p g p h 4 / p m s k p h 3 / s y n c 1 p h 2 / s y n c 0 / p m i p h 1 / e x i 1 p h 0 / e x i 0 p g 7 / r f g 1 p g 6 / r f g 0 p b 1 / p p o 0 0 9 / p p o 1 0 9 p b 0 / p p o 0 0 8 / p p o 1 0 8 p a 7 / p p o 0 0 7 / p p o 1 0 7 p a 6 / p p o 0 0 6 / p p o 1 0 6 p a 5 / p p o 0 0 5 / p p o 1 0 5 p a 4 / p p o 0 0 4 / p p o 1 0 4 p a 3 / p p o 0 0 3 / p p o 1 0 3 p a 2 / p p o 0 0 2 / p p o 1 0 2 p a 1 / p p o 0 0 1 / p p o 1 0 1 p a 0 / p p o 0 0 0 / p p o 1 0 0 v s s v d d n c p j 7 / a n 1 1 / k s 1 5 p j 6 / a n 1 0 / k s 1 4 p j 5 / a n 9 / k s 1 3 p j 4 / a n 8 / k s 1 2 p j 3 / a n 7 / k s 1 1 p j 2 / a n 6 / k s 1 0 p j 1 / a n 5 / k s 9 p e 7 p f 0 / e c 0 / i n t 0 p f 1 / e c 2 / i n t 1 p f 2 / c s 1 / n m i / c i n t p f 3 / s i 1 / i n t 2 p f 4 / s o 1 p f 5 / s c k 1 p f 6 / t 1 p f 7 / t 2 r s t v s s x t a l e x t a l v d d p g 0 / p w m 0 p g 1 / p w m 1 p g 2 / p w m 2 p g 3 / p w m 3 p g 4 / d a 0 p g 5 / d a 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 7 0 6 9 6 8 6 7 6 3 6 4 6 5 6 6 6 1 6 2 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 1 8 1 8 2 8 3 8 4 8 8 8 7 8 6 8 5 8 9 9 0 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 1 9 2 9 3 note) 1. vss (pins 15, 41, 72 and 90) must be connected to gnd. 2. v dd (pins 44 and 89) must be connected to v dd . 3. nc (pin 88) is left open.
? 4 CXP912032 pin configuration 2 (top view) 100-pin lqfp package p b 4 / p p o 0 1 2 p b 5 / p p o 0 1 3 p b 6 / p p o 0 1 4 p b 7 / p p o 0 1 5 p c 0 / p p o 0 1 6 p c 1 / p p o 0 1 7 p c 2 / p p o 0 1 8 p c 3 / r t o 0 p c 4 / r t o 1 p c 5 / r t o 2 p c 6 / r t o 3 p c 7 / r t o 4 v s s p d 0 / k s 0 p d 1 / k s 1 p d 2 / k s 2 p d 3 / k s 3 p d 4 / k s 4 p d 5 / k s 5 p d 6 / k s 6 p d 7 / k s 7 p e 0 p e 1 p e 2 p e 3 a v s s a n 3 a n 2 a n 1 p i 7 / a n 0 v s s p i 6 / x o u t p i 5 / o s c o p i 4 / p c k / o s c i p i 3 / c s 2 / p o p i 2 / s c k 2 p i 1 / s o 2 p i 0 / s i 2 s c k 0 s o 0 s i 0 c s 0 p h 7 / c f g p h 6 / d f g p h 5 / d p g p h 4 / p m s k p h 3 / s y n c 1 p h 2 / s y n c 0 / p m i p h 1 / e x i 1 p h 0 / e x i 0 p b 3 / p p o 0 1 1 p b 2 / p p o 0 1 0 p b 1 / p p o 0 0 9 / p p o 1 0 9 p b 0 / p p o 0 0 8 / p p o 1 0 8 p a 7 / p p o 0 0 7 / p p o 1 0 7 p a 6 / p p o 0 0 6 / p p o 1 0 6 p a 5 / p p o 0 0 5 / p p o 1 0 5 p a 4 / p p o 0 0 4 / p p o 1 0 4 p a 3 / p p o 0 0 3 / p p o 1 0 3 p a 2 / p p o 0 0 2 / p p o 1 0 2 p a 1 / p p o 0 0 1 / p p o 1 0 1 p a 0 / p p o 0 0 0 / p p o 1 0 0 v s s v d d n c p j 7 / a n 1 1 / k s 1 5 p j 6 / a n 1 0 / k s 1 4 p j 5 / a n 9 / k s 1 3 p j 4 / a n 8 / k s 1 2 p j 3 / a n 7 / k s 1 1 p j 2 / a n 6 / k s 1 0 p j 1 / a n 5 / k s 9 p j 0 / a n 4 / k s 8 a v d d a v r e f p e 4 p e 5 p e 6 p e 7 p f 0 / e c 0 / i n t 0 p f 1 / e c 2 / i n t 1 p f 2 / c s 1 / n m i / c i n t p f 3 / s i 1 / i n t 2 p f 4 / s o 1 p f 5 / s c k 1 p f 6 / t 1 p f 7 / t 2 r s t v s s x t a l e x t a l v d d p g 0 / p w m 0 p g 1 / p w m 1 p g 2 / p w m 2 p g 3 / p w m 3 p g 4 / d a 0 p g 5 / d a 1 p g 6 / r f g 0 p g 7 / r f g 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 1 7 6 7 7 7 8 7 9 8 0 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 8 1 8 2 8 3 8 4 8 8 8 7 8 6 8 5 8 9 9 0 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 1 9 2 9 3 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 7 0 6 9 6 8 6 7 6 3 6 4 6 5 6 6 6 1 6 2 7 1 7 2 7 3 7 4 7 5 note) 1. vss (pins 13, 39, 70 and 88) must be connected to gnd. 2. v dd (pins 42 and 87) must be connected to v dd . 3. nc (pin 86) is left open.
? 5 CXP912032 pin configuration 3 (top view) 104-pin lfbga package a 1 1 a 3 a 1 3 a 4 a 5 a 6 a 7 a 8 a 9 a 1 0 a 1 b 1 1 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 1 0 c 2 c 1 2 c 1 3 c 4 c 5 c 6 c 7 c 8 c 9 c 1 0 c 1 d 1 1 d 2 d 1 2 d 3 d 1 3 d 1 e 1 1 e 2 e 1 2 e 3 e 1 3 e 1 f 1 1 f 2 f 1 2 f 3 f 1 3 f 1 g 1 1 g 2 g 1 2 g 3 g 1 3 g 1 h 1 1 h 2 h 1 2 h 3 h 1 3 h 1 j 1 1 j 2 j 1 2 j 3 j 1 3 j 1 k 1 1 k 2 k 1 2 k 3 k 1 3 k 1 l 2 l 1 2 l 1 3 l 4 l 5 l 6 l 7 l 8 l 9 l 1 0 l 1 m 1 1 m 3 m 4 m 5 m 6 m 7 m 8 m 9 m 1 0 n 1 1 n 3 n 1 3 n 4 n 5 n 6 n 7 n 8 n 9 n 1 0 n 1 n c 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 a b c d e f g h j k l m n p b 1 p a 7 p a 4 p a 1 v s s n c p j 5 p j 2 p j 0 n c p b 2 p b 0 p a 5 p a 2 v d d p j 7 p j 4 p j 1 a v d d p b 6 p b 5 p b 3 p a 6 p a 3 p a 0 p j 6 p j 3 a v r e f a n 2 p c 0 p b 4 a v s s p i 7 p c 3 p c 1 v s s p i 5 p c 6 p c 4 p i 4 p i 2 v s s p d 0 p i 1 p i 0 p d 1 p d 3 c s 0 s o 0 p d 4 p d 6 p h 5 p h 7 p d 7 p e 3 p h 0 p h 4 p e 1 p e 4 p f 1 p f 4 v s s v d d p g 2 p g 7 p h 2 p e 5 p e 7 p f 2 p f 5 p f 7 e x t a l p g 1 p g 4 p g 6 n c p e 6 p f 0 p f 3 p f 6 r s t x t a l p g 0 p g 3 p g 5 n c p e 2 p e 0 p d 5 p d 2 p c 7 p c 5 p c 2 p b 7 a n 3 p h 1 p h 3 p h 6 s i 0 s c k 0 p i 3 p i 6 a n 1 note) 1. vss (pins a7, e11, g1 and l7) must be connected to gnd. 2. v dd (pins b7 and l8) must be connected to v dd . 3. nc (pins a1, a13, n1, n13 and a8) are left open. 4. a1, a13, n1 and n13 pins are reinforced balls.
? 6 CXP912032 output / real time output / real time output output / real time output / real time output output / real time output output / real time output output / real time output i/o i/o (port a) 8-bit output port. data is gated with ppo0 and ppo1 contents by or-gate and they are output. (8 pins) (port b) 8-bit output port. data is gated with ppo0 and ppo1 contents by or- gate and they are output. (8 pins) (port c) 8-bit i/o port. i/o can be specified by bit unit. data is gated with ppo0 or rto contents by or- gate and they are output. (8 pins) (port d) 8-bit i/o port. i/o can be specified by bit unit. standby release input function can also be specified by bit unit. can drive 12ma sync current when v dd = 5v. (8 pins) (port e) 8-bit i/o port. i/o can be specified by bit unit. can drive 12ma sync current when v dd = 5v. (8 pins) (port f) 8-bit port. lower 4 bits are for input; upper 4 bits are for output. (8 pins) programmable pattern generator (ppg0, ppg1) output. functions as high-precision real-time pulse output port. (ppg0 19 pins, ppg1 10 pins) real-time pulse generator (rtg) output. functions as high-precision real-time pulse output port. (5 pins) symbol i/o functions pa0/ppo000 /ppo100 to pa7/ppo007 /ppo107 pb0/ppo008 /ppo108 pb1/ppo009 /ppo109 pb2/ppo010 to pb7/ppo015 pc0/ppo016 to pc2/ppo018 pc3/rto0 to pc7/rto4 pd0 to pd7 pe0 to pe7 pf0/ec0/ int0 input / input / input input / input / input input / input / input / input input / input / input pf1/ec2/ int1 pf2/cs1/ nmi/cint pf3/si1/int2 pf4/so1 pf5/sck1 pf6/t1 pf7/t2 output / output output / i/o output / output output / output pin description external event input for timer/counter. (2 pins) serial data (ch1) input. serial data (ch1) output. serial data (ch1) i/o. 8-bit timer/counter output. 16-bit capture timer/counter output. input to request external interruption. active at the falling edge. serial chip select (ch1) input. input to request external interruption. active at the falling edge. (2 pins) input to request non-maskable interruption. active at the falling edge. external capture input for 16-bit timer/counter.
? 7 CXP912032 pg0/pwm0 pg1/pwm1 pg2/pwm2 pg3/pwm3 pg4/da0 pg5/da1 pg6/rfg0 pg7/rfg1 ph0/exi0 ph1/exi1 ph2/ sync0/pmi ph3/sync1 ph4/pmsk ph5/dpg ph6/dfg ph7/cfg sck0 so0 si0 cs0 pi0/si2 pi1/so2 pi2/sck2 pi3/cs2/po pi4/pck/ osci pi5/osco pi6/xout pi7/an0 an1 to an3 pj0/an4 to pj7/an11 output / output output / output output / output output / output output / output output / output input / input input / input input / input input / input input / input / input input / input input / input input / input input / input input / input i/o output input input i/o / input i/o / output i/o / i/o i/o / input / output input / input / input input / output input / output input / input input i/o / input 14-bit pwm output. (4 pins) da gate pulse output. (2 pins) reel fg input. (2 pins) external input for frc capture unit. (2 pins) composite sync signal input. (2 pins) mask input for pulse cycle measurement circuit. drum pg input. drum fg input. capstan fg input. serial data (ch2) input. serial data (ch2) output. serial clock (ch2) i/o. general-purpose prescaler external clock input. clock output from clock generator or general-purpose prescaler. serial clock (ch0) i/o. serial data (ch0) output. serial data (ch0) input. serial chip select (ch0) input. pulse input for pulse cycle measurement circuit. (port g) 8-bit port. lower 6 bits are for output; upper 2 bits are for input. (8 pins) (port h) 8-bit input port. (8 pins) (port i) 8-bit port. lower 4 bits are for i/o; upper 4 bits are for input. lower 4 bits can be specified by bit unit. (8 pins) (port j) 8-bit i/o port. i/o can be specified by bit unit. standby release input function can also be specified by bit unit. (8 pins) analog input for a/d converter. (12 pins) serial chip select (ch2) input. general-purpose prescaler output. symbol i/o functions connects a crystal for general- purpose prescaler clock oscillation. (mask option)
? 8 CXP912032 extal xtal rst av dd av ref av ss v dd v ss input output i/o input connects a crystal for system clock oscillation. when the clock is supplied externally, input it to extal and input an opposite phase clock to xtal. system reset. active at "l" level. positive power supply for a/d converter. reference voltage input for a/d converter. a/d converter gnd. positive power supply. all three v dd pins must be connected to the positive power supply. gnd. all four v ss pins must be connected to gnd. symbol i/o functions
? 9 CXP912032 10 pins hi-z hi-z after a reset pa0/ppo000/ ppo100 to pa7/ppo007/ ppo107 pb0/ppo008/ ppo108 to pb1/ppo009/ ppo109 pc0/ppo016 to pc2/ppo018 pc3/rto0 to pc7/rto4 hi-z pd0/ks0 to pd7/ks7 a a a a a a a a a a a a p p o 0 d a t a d a t a b u s o u t p u t b e c o m e s a c t i v e f r o m h i - z b y w r i t i n g d a t a t o p o r t r e g i s t e r . p o r t a o r p o r t b d a t a r d p p o 1 d a t a a a a a a a a a a a a a p p o 0 d a t a d a t a b u s o u t p u t b e c o m e s a c t i v e f r o m h i - z b y w r i t i n g d a t a t o p o r t r e g i s t e r . p o r t b d a t a r d p p o 0 o r r t o d a t a d a t a b u s r d ( p o r t c ) a a a a a a a a a a p o r t c d i r e c t i o n a a a a a a a a p o r t c d a t a i n p u t p r o t e c t i o n c i r c u i t i p ( e v e r y b i t ) a a " 0 " a f t e r a r e s e t d a t a b u s r d a a a a a a a a a a p o r t d d i r e c t i o n a a a a a a a a p o r t d d a t a i p ( e v e r y b i t ) a a * s t a n d b y r e l e a s e " 0 " a f t e r a r e s e t a a a a a a a a a a p o r t d s t a n d b y r e l e a s e d a t a a a a a e d g e d e t e c t i o n * l a r g e c u r r e n t d r i v e t r a n s i s t o r 6 pins hi-z pb2/ppo010 to pb7/ppo015 i/o circuit format for pins port a port b pin circuit format 8 pins 8 pins port b port c port d
? 10 CXP912032 8 pins hi-z hi-z after a reset pe0 to pe7 pf2/cs1/ nmi/cint hi-z pf4/so1 d a t a b u s r d a a a a a a a a a p o r t e d i r e c t i o n a a a a a a a a p o r t e d a t a i p ( e v e r y b i t ) a a a a * " 0 " a f t e r a r e s e t * l a r g e c u r r e n t d r i v e t r a n s i s t o r a a a a a a i p r d ( p o r t f ) d a t a b u s s c h m i t t t r i g g e r i n p u t i n t e r r u p t c i r c u i t a n d t i m e r / c o u n t e r o r s i o a a a i p r d ( p o r t f ) s c h m i t t t r i g g e r i n p u t a a a a a a a a a a p o r t f f u n c t i o n s e l e c t i o n i n t e r r u p t c i r c u i t t i m e r / c o u n t e r o r s i o d a t a b u s " 0 " a f t e r a r e s e t a a a a a a a a a a a a m p x d a t a b u s r d ( p o r t f ) a a a a a a a a a p o r t f f u n c t i o n s e l e c t i o n s o 1 f r o m s i o " 0 " a f t e r a r e s e t h i - z c o n t r o l a a a a a a a a p o r t f d a t a 3 pins hi-z pf0/ec0/int0 pf1/ec2/int1 pf3/si1/int2 port e pin circuit format 1 pin 1 pin port f port f port f
? 11 CXP912032 1 pin hi-z hi-z after a reset pf5/sck1 pg6/rfg0 pg7/rfg1 hi-z ph0/exi0 ph1/exi1 ph2/sync0/pmi ph3/sync1 ph4/pmsk ph5/dpg ph6/dfg ph7/cfg a a a a a a a a a a a a m p x d a t a b u s r d ( p o r t f ) a a a a a a a a p o r t f f u n c t i o n s e l e c t i o n i n t e r n a l s e r i a l c l o c k f r o m s i o " 0 " a f t e r a r e s e t h i - z c o n t r o l a a a a p o r t f d a t a a a a a i p s i o s c h m i t t t r i g g e r i n p u t a a a a a a a a a a a a m p x d a t a b u s r d ( p o r t f ) a a a a a a a a a a a a p o r t f f u n c t i o n s e l e c t i o n t i m e r / c o u n t e r " 0 " a f t e r a r e s e t a a a a a a a a p o r t f d a t a " 1 " w h e n r e s e t a a a a a a a a m p x d a t a b u s r d ( p o r t g ) a a a a a a a a p o r t g f u n c t i o n s e l e c t i o n d a g a t e o u t p u t o r p w m o u t p u t " 0 " a f t e r a r e s e t h i - z c o n t r o l a a a a a a a a p o r t g d a t a a a a a a a a a i p r d ( p o r t g ) d a t a b u s s e r v o c i r c u i t s c h m i t t t r i g g e r i n p u t a a a a a a a a i p r d ( p o r t h ) d a t a b u s s e r v o c i r c u i t n o t e ) p h 2 / s y n c 0 / p m i a n d p h 3 / s y n c 1 c a n s e l e c t c m o s s c h m i t t t r i g g e r i n p u t o r t t l s c h m i t t t r i g g e r i n p u t w i t h t h e m a s k o p t i o n . s c h m i t t t r i g g e r i n p u t 2 pins "h" level hi-z pf6/t1 pf7/t2 pg0/pwm0 pg1/pwm1 pg2/pwm2 pg3/pwm3 pg4/da0 pg5/da1 port f pin circuit format 2 pins 8 pins port f port g 6 pins port g port h
? 12 CXP912032 2 pins hi-z hi-z after a reset cs0 si0 pi0/si2 hi-z pi1/so2 pi2/sck2 a a a a a a i p s i o s c h m i t t t r i g g e r i n p u t s o 0 o u t p u t e n a b l e a a a a s o 0 f r o m s i o s c k 0 o u t p u t e n a b l e a a a a i n t e r n a l s e r i a l c l o c k f r o m s i o a a i p e x t e r n a l s e r i a l c l o c k t o s i o s c h m i t t t r i g g e r i n p u t d a t a b u s r d ( p o r t i ) a a a a a a a a a p o r t i d i r e c t i o n a a a a a a a a p o r t i d a t a i p ( e v e r y b i t ) a a a a " 0 " a f t e r a r e s e t s i o s c h m i t t t r i g g e r i n p u t a a a a a a a a m p x a a a a a a a a p o r t i d a t a a a i p d a t a b u s r d ( p o r t i ) a a a a a a a a p o r t i f u n c t i o n s e l e c t i o n a a a a a a a a a m p x s c h m i t t t r i g g e r i n p u t s i o " 0 " a f t e r a r e s e t s i o a a a a a a a a p o r t i d i r e c t i o n " 0 " a f t e r a r e s e t n o t e ) o n l y p i 2 i s s c h m i t t t r i g g e r i n p u t . s i o ( p i 2 o n l y ) 1 pin hi-z hi-z so0 sck0 pin circuit format 1 pin 2 pins 1 pin port i port i
? 13 CXP912032 hi-z oscillation hi-z after a reset pi3/cs2/po pi4/pck/osci pi5/osco hi-z pi6/xout a a a a a a a m p x a a a a a a a a p o r t i d a t a a a a a i p d a t a b u s r d ( p o r t i ) a a a a a a a a p o r t i d i r e c t i o n a a a a a a a a p o r t i f u n c t i o n s e l e c t i o n g e n e r a l - p u r p o s e p r e s c a l e r " 0 " a f t e r a r e s e t " 0 " a f t e r a r e s e t s c h m i t t t r i g g e r i n p u t s i o a a a a a a a a i p a a a a o s c i o s c o a a a a a a a a p o r t i f u n c t i o n s e l e c t i o n " 0 " a f t e r a r e s e t g e n e r a l - p u r p o s e p r e s c a l e r a a a a a a a a a a a a m p x a a i p d a t a b u s r d ( p o r t i ) a a a a a a a a p o r t i f u n c t i o n s e l e c t i o n c l o c k g e n e r a t o r g e n e r a l - p u r p o s e p r e s c a l e r " 0 " a f t e r a r e s e t pin circuit format 2 pins 1 pin 1 pin port i port i port i fig. 1. a a a a a a i p r d ( p o r t i ) d a t a b u s g e n e r a l - p u r p o s e p r e s c a l e r p i 4 / p c k o r p i 5 n o t e ) t h e c i r c u i t f o r m a t i n f i g . 1 o r f i g . 2 c a n b e s e l e c t e d w i t h t h e m a s k o p t i o n . fig. 2.
? 14 CXP912032 a a a a a a a a i p a a a a e x t a l x t a l d i a g r a m s h o w s c i r c u i t c o m p o s i t i o n d u r i n g o s c i l l a t i o n . f e e d b a c k r e s i s t o r i s r e m o v e d d u r i n g s t o p m o d e . s t o p s i g n a l hi-z osillation after a reset an1 to an3 pi7/an0 extal xtal a a a a a a a a a a p o r t j d a t a a a i p d a t a b u s r d ( p o r t j ) a a a a a a p o r t j d i r e c t i o n a a a a a a a a p o r t j i n p u t s e l e c t i o n " 0 " a f t e r a r e s e t " 0 " a f t e r a r e s e t i n p u t m u l t i p l e x e r a / d c o n v e r t e r s t a n d b y r e l e a s e hi-z pj0/an4/ks8 to pj7/an11/ks15 "l" level rst a a a a a a i p a / d c o n v e r t e r i n p u t m u l t i p l e x e r hi-z a a a a a a i p a / d c o n v e r t e r i n p u t m u l t i p l e x e r a a a a a a a a p o r t i f u n c t i o n s e l e c t i o n " 0 " a f t e r a r e s e t d a t a b u s r d ( p o r t i ) a a a a a a a a i p s c h m i t t t r i g g e r i n p u t p u l l - u p r e s i s t o r m a s k o p t i o n o p f r o m e m u l a t o r ( c x p 9 1 2 0 0 0 o n l y ) pin circuit format 2 pins 1 pin 3 pins port j 1 pin 8 pins port i
? 15 CXP912032 * 1 av dd and v dd must be the same voltage. * 2 v in and v out must not exceed v dd + 0.3v. * 3 nch transistors of pd and pe output ports are the large current drive transistors. note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. supply voltage input voltage output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd av dd av ss v in v out i oh i oh i ol i olc i ol topr tstg p d ?.3 to +7.0 avss to +7.0 * 1 ?.3 to +0.3 ?.3 to +7.0 * 2 ?.3 to +7.0 * 2 ? ?0 15 20 130 ?0 to +75 ?5 to +150 600 380 500 v v v v v ma ma ma ma ma c c mw total for all output pins all pins excluding large current output pins large current output pins * 3 total for all output pins qfp package lqfp package lfbga package item symbol rating unit remarks absolute maximum ratings (v ss = 0v reference)
? 16 CXP912032 analog voltage high level input voltage low level input voltage operating temperature supply voltage 5.5 5.5 5.5 5.5 v dd v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.2v dd 0.8 0.4 +75 v v v v v v v v v v v v v c item symbol min. max. unit remarks 2.7 2.7 2.5 2.7 0.7v dd 0.8v dd 2.2 v dd ?0.4 0 0 0 ?.3 ?0 av dd v ih v ihs v ihts v ihex v il v ils v ilts v ilex topr guaranteed operation range for high-speed mode (1/2 frequency dividing clock) guaranteed operation range for low-speed mode (1/16 frequency dividing clock) guaranteed data hold range during stop mode * 1 * 2 cmos schmitt trigger input * 3 ttl schmitt trigger input * 4 , * 7 extal * 5 * 2 * 2 , * 6 cmos schmitt trigger input * 3 ttl schmitt trigger input * 4 , * 7 extal v dd * 1 av dd and v dd must be the same voltage. * 2 pc, pd, pe, pi1, pi3 to pi7, pj for normal input port * 3 cs0, si0, sck0, rst, pf0/ec0/int0, pf1/ec2/int1, pf2/cs1/nmi/cint, pf3/si1/int2, pf5/sck1, pg6/rfg0, pg7/rfg1, ph (ph2 and ph3 when cmos schmitt trigger input is selected with the mask option), pi0/si2, pi2/sck2. * 4 ph2 and ph3 (when ttl schmitt trigger input is selected with the mask option). * 5 specified only during external clock input. * 6 when the supply voltage (v dd ) is within the range of 2.7 to 3.6v. * 7 when the supply voltage (v dd ) is within the range of 4.5 to 5.5v. recommended operating conditions (v ss = 0v reference)
? 17 CXP912032 (ta = ?0 to +75 c, v ss = 0v reference) dc characteristics item high level output voltage v oh pa to pe, pf6 to pf7, pg0 to pg5, pi0, pi3, pi6, pj pf4, pf5, pi1, pi2, so0, sck0 pa to pc, pf4 to pf7, pg0 to pg5, pi0 to pi3, pi6, pj, so0, sck0, rst * 1 v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 2.7v, i oh = ?.15ma v dd = 2.7v, i oh = ?.5ma v dd = 4.5v, i oh = ?.0ma v dd = 3.0v, i oh = ?.0ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 2.7v, i ol = 1.2ma v dd = 2.7v, i ol = 1.6ma v dd = 4.5v, i ol = 12.0ma v dd = 2.7v, i ol = 5.0ma v dd = 5.5v, v ih = 5.5v v dd = 3.6v, v ih = 3.6v v dd = 5.5v, v il = 0.4v v dd = 3.6v, v il = 0.3v v dd = 5.5v, v il = 0.4v v dd = 3.6v, v il = 0.3v v dd = 5.5v, v i = 0, 5.5v v dd = 3.6v, v i = 0, 3.6v 20mhz crystal oscillation (c 1 = c 2 = 10pf), v dd = 5v 10% 20mhz crystal oscillation (c 1 = c 2 = 10pf), v dd = 3.3v 0.3v 20mhz crystal oscillation (c 1 = c 2 = 10pf), v dd = 5v 10%, sleep mode 20mhz crystal oscillation (c 1 = c 2 = 10pf), v dd = 3.3v 0.3v, sleep mode v dd = 5.5v, stop mode v dd = 3.6v, stop mode clock 1mhz 0v for all pins excluding measured pins 4.0 3.5 2.4 2.0 3.6 2.0 0.5 0.3 ?.5 ?.3 ?.5 ?.9 40 22 8 4.5 10 0.4 0.6 0.3 0.5 1.5 1.0 40 20 ?0 ?0 ?00 ?00 10 10 65 40 14 8 10 10 20 v v v v v v v v v v v v a a a a a a a a ma ma ma ma a a pf pd, pe extal rst * 2 pa to pj, an1 to an3, cs0, si0, so0, sck0 rst * 2 v dd , v ss pins other than v dd , v ss , av dd , av ss v ol i ihe i ile i ilr i iz i dd * 4 i dds1 * 5 i dds2 c in low level output voltage input current i/o leakage current supply current * 3 input capacitance symbol pin conditions min. typ. max. unit
? 18 CXP912032 * t sys indicates the three values below according to the upper two bits (cpu clock selected) of the clock control register clc (address: 0002feh). t sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") e x t a l t x h t x l t c f t c r 0 . 4 v v d d 0 . 4 v 1 / f c a a a a a a a a e x t e r n a l c l o c k e x t a l x t a l 7 4 h c 0 4 a a a a a a a a e x t a l x t a l c r y s t a l o s c i l l a t i o n p f 0 / e c 0 p f 1 / e c 2 t e h t e l t e f t e r 0 . 2 v d d 0 . 8 v d d ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise time, fall time event count input clock pulse width event count input clock rise time, fall time f c t xh , t xl t cr , t cf t eh , t el t er , t ef xtal, extal extal extal pf0/ec0, pf1/ec2 pf0/ec0, pf1/ec2 item symbol pin conditions unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 min. 1 1 20 20 t sys + 50 * t sys + 100 * 20 20 200 200 20 20 mhz mhz ns ns ns ns ns ns ms ms max. (ta = ?0 to +75 c, v ss = 0v reference) fig. 1. clock timing v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% fig. 2. clock applied conditions * 1 rst is specified only in evaluation mode. * 2 in rst, the input current is specified when pull-up resistor is selected; the leakage current is specified when no resistor is selected. * 3 when all output pins are open. * 4 when the upper two bits (cpu clock selected) of the clock control register clc (address: 0002feh) are set to "00" and the lsi is operated in high-speed mode (1/2 frequency dividing clock). * 5 when the clock generator output is not selected at pi6. fig. 3. event count clock timing
? 19 CXP912032 chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% t sys + 100 t sys + 100 2 t sys + 200 2 t sys + 200 16000/fc 16000/fc t sys + 100 t sys + 100 8000/fc ?50 8000/fc ?75 100 100 200 ? t sys 200 ? t sys t sys + 100 t sys + 100 t sys + 100 t sys + 100 2 t sys + 100 2 t sys + 125 8000/fc ?50 8000/fc ?75 t sys + 200 t sys + 250 t sys + 200 t sys + 250 t sys + 200 t sys + 250 t sys + 200 t sys + 250 t sys + 100 t sys + 150 50 100 note 1) t sys indicates the three values below according to the upper two bits (cpu clock selected) of the clock control register clc (address: 0002feh). t sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") note 2) the load condition for the sck output mode, so output delay time is 150pf when v dd = 5.0v 10% and 100pf when v dd = 3.0v 10%. (2) serial interface (ch0, ch1, ch2) (ta = ?0 to +75 c, v ss = 0v reference) item cs ? sck delay time cs - ? sck float delay time cs ? so delay time cs - ? so float delay time cs high level width sck cycle time sck high, low level width si input setup time (for sck - ) si input hold time (for sck - ) sck ? so delay time minimum interval time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh , t kl t sik t ksi t kso t int sck0, sck1, sck2 so0, so1, so2 so0, so1, so2 cs0, cs1, cs2 sck0, sck1, sck2 sck0, sck1, sck2 sck0, sck1, sck2 si0, si1, si2 si0, si1, si2 so0, so1, so2 sck0, sck1, sck2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns symbol pin min max. unit conditions
? 20 CXP912032 fig. 4. serial interface ch0, ch1, ch2 timing t k s i c s 0 c s 1 c s 2 s c k 0 s c k 1 s c k 2 0 . 2 v d d 0 . 8 v d d t w h c s t d c s k t d c s k f 0 . 8 v d d 0 . 2 v d d t k c y t k l t k h 0 . 8 v d d 0 . 2 v d d s i 0 s i 1 s i 2 t s i k t d c s o t k s o t d c s o f 0 . 8 v d d 0 . 2 v d d s o 0 s o 1 s o 2 s c k 0 s c k 1 s c k 2 0 . 8 v d d t i n t i n p u t d a t a o u t p u t d a t a
? 21 CXP912032 (3) a/d converter characteristics (ta = ?0 to +75 c, v dd = av dd = av ref = 3.0 to 5.5v, v ss = av ss = 0v reference) a n a l o g i n p u t l i n e a r i t y e r r o r v f t v z t 0 0 h 0 1 h f e h f f h d i g i t a l c o n v e r s i o n v a l u e ta = 25 c operation mode sleep mode stop mode v dd = av dd = 5.0v v dd = av dd = 3.0v v dd = av dd = 5.0v v dd = av dd = 3.0v v dd = av dd = 5.0v v dd = av dd = 3.0v v dd = 5.5v v dd = 3.6v v dd = 5.5v v dd = 3.6v ?0 ?0 4935 2955 200 t sys 14 t sys 0.9av dd 0 10 5 4975 2985 0.65 0.45 8 15 15 50 35 5015 3015 av dd av ref 1.2 0.8 10 10 bits lsb mv mv s s v v ma a item resolution linearity error zero transition voltage full-scale transition voltage conversion time sampling time reference input voltage analog input voltage av ref current v zt * 1 v ft * 2 t conv t samp v ref v ian i ref i refs av ref an0 to an11 av ref symbol pin min. typ. max. unit conditions * 1 v zt : value at which the digital conversion value changes from 00h to 01h and vice versa. * 2 v ft : value at which the digital conversion value changes from feh to ffh and vice versa. note) t sys indicates the three values below according to the upper two bits (cpu clock selected) of the clock control register clc (address: 0002feh). t sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") fig. 5. definition of a/d converter terms
? 22 CXP912032 external interruption high, low level width reset input low level width nmi int0 int1 int2 pd0 to pd7 rst 1 6 t sys * s s item symbol pin conditions min. max. unit t ih , t il t rsl (4) interruption and reset input (ta = ?0 to +75 c, v dd = 2.7 to 5.5v, v ss = 0v reference) 0 . 2 v d d 0 . 8 v d d t i h t i l n m i i n t 0 i n t 1 i n t 2 p d 0 t o p d 7 p j 0 t o p j 7 ( d u r i n g s t a n d b y r e l e a s e i n p u t ) ( f a l l i n g e d g e ) fig. 6. interruption input timing t r s l 0 . 2 v d d r s t fig. 7. rst input timing * t sys indicates the three values below according to the upper two bits (cpu clock selected) of the clock control register clc (address: 0002feh). t sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
? 23 CXP912032 external clock input pck t r = t f = 6ns external clock input pck t r = t f = 6ns v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% 33 33 (5) general-purpose prescaler item f pck t wh , t wl t r , t f t plh t phl t tlh t thl pck pck pck po po mhz ns ns ns ns ns ns symbol pin min. 80 130 60 90 50 100 20 40 typ. 12 12 200 200 130 220 100 150 100 280 40 80 max. unit conditions external clock input frequency external clock input pulse width external clock input rise time, fall time prescaler output delay time (for pck - ) prescaler output rise time, fall time note) po pin load condition: 50pf p c k p o 1 / f p c k t w h t f 0 . 2 v d d 0 . 8 v d d t w l 0 . 5 v d d t r 0 . 2 v d d 0 . 8 v d d 0 . 5 v d d t p l h t t l h t t h l t p h l (ta = ?0 to +75 c, vss = 0v reference) fig. 8. general-purpose prescaler timing
? 24 CXP912032 v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% v dd = 5.0v 10% v dd = 3.0v 10% (6) other (ta = ?0 to +75 c, v ss = 0v reference) item t cfh , t cfl t dfh , t dfl t dpw t dpr t rfh , t rfl t eih , t eil t pih , t pil t pmw t pmr t tlh t thl cfg dfg dpg dpg rfg0 rfg1 exi0 exi1 pmi pmsk pmsk xout when t sys = 2000/fc when the load is 50pf ns ns ns ns ns ns ns ns ns ns symbol pin min. 50 100 20 40 typ. 100 280 40 80 max. unit conditions cfg input high, low level width dfg input high, low level width dpg minimum pulse width dpg minimum removal time rfg input high, low level width exi input high, low level width pmi input high, low level width pmsk minimum pulse width pmsk minimum removal time xout output rise time, fall time t sys + 200 t sys + 200 1000/fc + 200 1000/fc + 200 50 50 50 50 t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 note) t sys indicates the three values below according to the upper two bits (cpu clock selected) of the clock control register clc (address: 0002feh). t sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
? 25 CXP912032 fig. 9. other timing 0 . 8 v d d c f g t c f h t c f l d f g t d f h t d f l r f g 0 r f g 1 t r f h t r f l 0 . 8 v d d t d p r t d p w t d p r d p g 0 . 2 v d d 0 . 8 v d d 0 . 2 v d d e x i 0 e x i 1 t e i h t e i l 0 . 8 v d d 0 . 2 v d d 0 . 8 v d d 0 . 2 v d d p m i t p i h t p i l 0 . 8 v d d t p m r t p m w t p m r p m s k 0 . 8 v d d 0 . 2 v d d x o u t 0 . 8 v d d 0 . 2 v d d t t l h t t h l
? 26 CXP912032 appendix c 2 c 1 a a a a a a a a a a a a a a a e x t a l x t a l m a i n c l o c k c 2 c 1 a a a a a a a a a a a a o s c i o s c o g e n e r a l - p u r p o s e p r e s c a l e r c l o c k m a s k o p t i o n manufacturer river eletec co., ltd. kinseki ltd. model hc-49/u03 hc-49/u (-s) fc (mhz) 12 16 20 12 16 20 10 10 10 10 c 1 (pf) c 2 (pf) c 1 (pf) c 2 (pf) 4 4 4 4 main clock general-purpose prescaler clock extal system operating voltage * reset pin pull-up resistor ph2 input circuit ph3 input circuit pi4/pi5 pin circuit 2.7 to 5.5v non-existent cmos schmitt trigger cmos schmitt trigger oscillation circuit 4.5 to 5.5v existent ttl schmitt trigger ttl schmitt trigger input pin item selection * select 4.5v to 5.5v when this lsi is used with a supply voltage range of 4.5v to 5.5v. note 1) use the general-purpose prescaler clock at 12mhz or less. note 2) crystals and capacitors should be placed near the lsi and wiring should be as short as possible. mask option table fig. 10. recommended oscillation circuit
? 27 CXP912032 1 / 2 f r e q u e n c y d i v i d i n g m o d e 1 / 4 f r e q u e n c y d i v i d i n g m o d e 1 / 8 f r e q u e n c y d i v i d i n g m o d e 1 / 1 6 f r e q u e n c y d i v i d i n g m o d e s l e e p m o d e 1 / 2 f r e q u e n c y d i v i d i n g m o d e 1 / 4 f r e q u e n c y d i v i d i n g m o d e 1 / 8 f r e q u e n c y d i v i d i n g m o d e 1 / 1 6 f r e q u e n c y d i v i d i n g m o d e s l e e p m o d e 2 3 4 5 6 5 0 4 0 3 0 2 5 2 0 1 5 1 0 8 6 5 4 3 v d d s u p p l y v o l t a g e [ v ] i d d s u p p l y c u r r e n t [ m a ] i d d v s . v d d ( f c = 2 0 m h z , t a = 2 5 c , t y p i c a l ) 0 5 1 0 1 5 2 0 f c s y s t e m c l o c k [ m h z ] i d d v s . f c ( v d d = 5 v , t a = 2 5 c , t y p i c a l ) i d d s u p p l y c u r r e n t [ m a ] 4 0 . 0 0 3 8 . 0 0 3 6 . 0 0 3 4 . 0 0 3 2 . 0 0 3 0 . 0 0 2 8 . 0 0 2 6 . 0 0 2 4 . 0 0 2 2 . 0 0 2 0 . 0 0 1 8 . 0 0 1 6 . 0 0 1 4 . 0 0 1 2 . 0 0 1 0 . 0 0 8 . 0 0 6 . 0 0 4 . 0 0 2 . 0 0 0 . 0 0 example of representative characteristics
? 28 CXP912032 package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e 2 3 . 9 0 . 4 q f p - 1 0 0 p - l 0 1 1 0 0 p i n q f p ( p l a s t i c ) 2 0 . 0 0 . 1 + 0 . 4 0 . 1 5 0 . 0 5 + 0 . 1 1 5 . 8 0 . 4 1 7 . 9 0 . 4 1 4 . 0 0 . 1 + 0 . 4 2 . 7 5 0 . 1 5 + 0 . 3 5 a 0 . 6 5 m 0 . 1 3 q f p 1 0 0 - p - 1 4 2 0 1 . 7 g 1 1 0 0 8 1 8 0 5 1 5 0 3 1 3 0 0 . 3 0 . 1 + 0 . 1 5 d e t a i l a 0 t o 1 0 0 . 8 0 . 2 ( 1 6 . 3 ) 0 . 1 5 0 . 1 0 . 0 5 + 0 . 2 s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 a l l o y p a c k a g e s t r u c t u r e d e t a i l a l q f p - 1 0 0 p - l 0 1 l q f p 1 0 0 - p - 1 4 1 4 1 0 0 p i n l q f p ( p l a s t i c ) 1 6 . 0 0 . 2 * 1 4 . 0 0 . 1 7 5 5 1 5 0 2 6 2 5 1 7 6 0 . 5 0 . 1 8 0 . 0 3 + 0 . 0 8 ( 0 . 2 2 ) a 1 . 5 0 . 1 + 0 . 2 0 . 1 2 7 0 . 0 2 + 0 . 0 5 0 . 5 0 . 2 ( 1 5 . 0 ) 0 t o 1 0 0 . 1 0 . 1 0 . 5 0 . 2 1 0 0 0 . 1 n o t e : d i m e n s i o n * d o e s n o t i n c l u d e m o l d p r o t r u s i o n . 0 . 8 g 0 . 1 3 m
? 29 CXP912032 package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a s s p a c k a g e s t r u c t u r e l f b g a - 1 0 4 p - 0 1 o r g a n i c s u b s t r a t e 0 . 5 g p a c k a g e m a t e r i a l b o a r d t r e a t m e n t t e r m i n a l m a t e r i a l c o p p e r - c l a p r a m i n a t e s o l d e r 1 0 4 p i n l f b g a l f b g a 1 0 4 - p - 1 3 1 3 s 0 . 1 0 1 . 6 m a x s s 0 . 2 0 s 0 . 2 0 1 3 . 0 1 3 . 0 f 0 . 1 5 a s f 0 . 1 5 b s x 4 p i n 1 i n d e x 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 0 4 f 0 . 4 0 0 . 0 5 f 0 . 0 8 m s a b a b 0 . 8 a b c d e f g h j k l m n 0 . 8 1 . 7 1 . 7 s o l d e r b a l l 0 . 3

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